A. Field of the Invention
The present invention pertains to the electronic signal processing art and in particular to a programmable frequency divider suitable for use in a frequency synthesizer.
B. Description of the Prior Art
Programmable frequency dividers are known in the electronic processing art, particularly in the frequency synthesizer field. Frequency synthesizers commonly employ standard phase locked loop circuitry wherein a controlled oscillator signal is divided by a loop divider. The output of the loop divider is fed back and compared in a phase comparator to a reference frequency signal. The phase comparator generates a control signal which is then coupled to the controlled oscillator, thereby providing an output signal from the controlled oscillator which has the desired frequency.
Previous techniques employed in digital frequency synthesizers have used a single programmable divider as the loop divider. This approach, however, has very serious problems in synthesizers used at very high frequencies. A suitable divider for a high frequency synthesizer would require a large divider using high speed logic which would make it difficult to interface with the rest of the synthesizer, and would be very expensive to integrate due to the large chip size required. A more serious disadvantage is the fact that such a loop divider would draw a very large current making it unsuitable for mobile or portable applications.
One approach to the solution of these problems is the use of a high speed prescaler of limited size followed by a lower speed programmable counter. This permits use of lower speed logic for most of the loop divider reducing cost and current drain. However, a major disadvantage is that the loop divider using a fixed prescaler can be reprogrammed only in increments equal to multiples of the prescaler modulus.
To deal with this problem another technique has been developed using a high speed dual modulus prescaler of limited size, and two programmable counters. The first counter is programmed to divide the output of the dual modulus prescaler by a number N.sub.p. The second counter, often referred to as a "swallow counter," is programmed to divide the output of the dual modulus prescaler by a number A, which is less than N.sub.p. The output of the controlled oscillator is divided by the prescaler, with first modulus P+1 and applied to both counters. When the count in the two counters reaches the number A, the swallow counter actuates the dual modulus prescaler to a new modulus P. The output of the prescaler then continues to be divided by the first counter. At the end of the count N.sub.P the counters must be reset. The total divisor of the loop divider N.sub.T is given by the formula: EQU N.sub.T =(P+1)A+P(N.sub.p -A)=PN.sub.p +A
as discussed at page 1003 of the Motorola McMoss Handbook, printed 1974 by Motorola, Inc. From the above equation it can be seen that the dual modulus prescaler approach permits a change in the divide ratio in increments of one merely by reprogramming the value of A.
This dual modulus prescaler approach is limited in frequency by the fact that the counters must be reset at the end of the count. This problem can be partially compensated for by the use of complicated logic circuitry such as the Motorola type MC12014 control logic circuit presently available in the marketplace. This approach is rather costly and requires substantial current drain because of the large number of components and complexity of the control logic. Furthermore, it is difficult to integrate an entire loop divider of this type on a single chip. Thus, it is desireable to provide a divider circuit which can be used in a high frequency synthesizer which uses fewer parts, draws less current and is consequently less expensive to manufacture and yet adaptable for integration on a single chip.